The present invention relates to phase interpolators, and more particularly, to triangulating phase interpolators.
FIG. 1 is a schematic block diagram of a phase interpolator which suffers from several disadvantages, including the following:                the symmetric PMOS loads used are vulnerable to M/S ratio errors and differential offsets;        injection of switching noise directly into differential amplifiers;        reduction of headroom by current source/switch device stack;        use of input clock multiplexers creates further potential switching noise problems.        
In addition when using conventional phase interpolation techniques there is a degradation of linearity when the separation of the reference clock phases is increased from 45° to 90°, thereby limiting the use of the FIG. 1 phase interpolator.
There is a need for an improved phase interpolator which can mitigate the described disadvantages.